1. Field of the Invention
The present invention relates to a loosely coupled multi-processor system and, more particularly, to a high-speed system for the exclusive shared among systems.
2. Description of the Prior Art
Tightly coupled multi-processors and loosely coupled multi-processors are frequently used as a system for coupling a plurality of processors. The former are characterized in that a main storage is shared among the processors and controlled by one OS (Operating System), and the latter are characterized in that the processors are equipped with independent main storages (i.e., not shared) under independent OSes and coupled through a shared input/output unit called DASD (Direct Access Storage Device). This input/output unit is composed of a sequential access memory such as a disk device.
The latter systems of the prior art are discussed on pp. 459 to 462. "Computer Architecture and Parallel Processing" of Mc Graw-Hill Book Company By K. Hwang, F. A. Briggs and on pp. 154 to 173, "Multiple Virtual Storage Operating System" of Ohm Kabushiki Kaisha by Hajime Kamata, 1983.
FIG. 2 shows the structure of one example of such loosely coupled multi-processor system. In FIG. 2: reference numerals 1 to 4 designated instruction processors #1, #2, #3 and #4; numerals 5 and 6 system controllers #1 and #2; numerals 7 and 9 main storages; and numerals 8 and 10 input/output processors. Numerals 11A and 11C designate non-shared input/output units; numeral 11B a shared DASD; and numeral 90 a channel-to-channel adaptor (CTCA). The instruction processors #1 and #2 have a tightly coupled multi-processor structure having the main storage 7 and the input/output processor 8 connected to the processors #1 and #2 through the system controller #1. Likewise, the instruction processor #3 and #4 employ a tightly coupled multi-processor structure having the main storage 9 and the input/output processor 10 connected to the processors #3 and #4 through the system controller #2. Each sub-system composed of the two instruction processors, the system controller, the main storage, the input/output processor and the non-shared input/output unit is called a "processor sub-system". In FIG. 2, these two processor sub-systems constitute together the loosely coupled multi-processor system coupled through the CTCA 90 and the shared DASD 11B.
An exclusive control is necessary for controlling the input/output unit 11B shared in the system. In case each processor (e.g., #1) updates the content of the shared input/output unit 11B, it requests, in advance, another processor sub-system, to give permission to use the shared unit 11B through the system controller (e.g., #1), the input/output processor (e.g., 8) and CTCA 90. The requested processor sub-system gives the permission through the CTCA 90 if it is not using the shared unit 11B. The same sub-system does not give permission if it is using the shared DASD 11B. With the permission, the process # subsequently accesses the shared input/output unit 11B. Otherwise, this access is inhibited until the requested processor sub-system informs the process #1 of the end of use of the shared input/output unit 11B through the CTCA 90. Thus, the exclusive control of the shared input/output unit 11B is accomplished through the CTCA.
This CTCA is also used for the communications between the processor sub-systems.
In the prior art thus far described, an access is made through the CTCA in the case of using the shared input/output unit and for the communications between the processor sub-systems. The CTCA is one of the input/output units and requires a channel (input/output) program. The operation of the channel program requires execution of a start I/O instruction. This start I/O instruction is accompanied by the execution of an ordinary type preparatory system control program so that many instructions have to be processes by an instruction processor.